1. Field of the Invention
The invention relates generally to the semiconductor devices. More particularly, this invention relates to a semiconductor device with high breakdown voltage and low on-resistance implemented with a three-dimensional charge balancing configuration for uniformly distributing crystals as uniformly distributed charge coupling elements distributed over the trenches that extend into the drift drain region of the high-voltage device such as cathode of diode, drain of MOSFET, Collector of Bipolar, etc.
2. Description of the Prior Art
Conventional technologies of designing and manufacturing semiconductor devices in striving to achieve a high breakdown voltage as well as low on resistance are still confronted with challenges and limitations. Specifically, breakdown in a high voltage device is often caused by concentration of electric fields. The concentration of the electric fields frequently occurs in the edges or corners of an electric device or at particular junction points. For the purpose of increasing the breakdown voltage, devices of larger form factors or implementation of materials with higher resistivity may be used. However, such devices, even with increased breakdown voltages, lead to another unfavorable performance parameter of a higher on-resistance. These two competitive and inherent conflicting design considerations to those of ordinary skill in the art become a technical difficulty that cannot be conveniently resolved. As will be briefly reviewed below, many device configurations and manufacturing methods have been disclosed in attempt to resolve the problems caused by this technical difficulty.
Designs and manufacturing methods have been disclosed to achieve a high breakdown voltage in three basic types of device structures. The first type of structure is implemented with a typical vertical DMOS structure wherein a high breakdown voltage is achieved by maintaining a low dopant concentration of the drain drift region as that shown in FIG. 1A. In this vertical DMOS device, the N-epitaxial region that constitutes a N-drift region is kept at a relatively low dopant concentration. FIG. 1B is a “Johnson Limit” diagram to illustrate the “figure of merit” of this device by showing the resistance Rsp as a function of breakdown voltage BV. As illustrated in FIG. 1B, there is no enhancement in the breakdown voltage beyond the 1D (one-dimensional) theoretical figure of merit shown in the Johnson Limit diagram due to the fact that there is no charge balance of the field shaping. Even though such device structure generally has lower manufacturing costs because of simpler configuration and processes, the devices of this type of structure have large die size as that required to achieve both the high BV and low on-resistance. This type of device structures is therefore not suitable for modern electronic devices that frequently require miniaturized size in order to satisfy the convenient portability requirements.
The second type of device structure is a two-dimensional charge balance structure. This type of structures has an advantage over the first type of structure because the breakdown voltage enhancement is achieved beyond the estimated Johnson limit criteria. One of the embodiments for such structure is through a super-junction configuration to achieve a reduced Rsp by increasing the drain doping while maintaining the desired breakdown voltage. FIG. 2A shows device where P-type vertical columns are formed in the drain thus resulting in lateral and complete depletion of the drain at a high voltage. Meanwhile the P-columns serve the function to pinch off and shield the channel from the high voltage at the drain terminal disposed on the bottom of the N+ substrate. FIG. 2B is a diagram that shows the improved performance achieved because of the charge balance effect. FIG. 2C shows a floating island configuration implemented to increase the breakdown voltage and lower the resistance by increasing the dopant concentration of a given breakdown voltage. FIG. 2D shows the further improvement achieved by this device. The super junction configuration as shown relies on the depletion of the P-regions to shield the gate/channel from the drain at a high voltage. FIGS. 2E-1 and 2E-2 show another device configuration implemented with oxide bypass to achieve BV enhancement and resistance reduction. The oxide bypass is formed as a vertical field plate inside the drain instead of the P-regions. However, the field plate has the drawback that the entire drain to source voltage is across the oxide that separates the field plate from the semiconductor thus requiring thicker oxide layers. FIG. 2F is a diagram show the figure of merit improvement. FIG. 2G shows another device configuration with enhanced performance of higher breakdown voltage implemented with deep trenches filled with semi-insulating polysilicon (SiPOS) as that disclosed by Boden in U.S. Pat. No. 6,452,230 and Kinzer in U.S. Pat. No. 6,608,350. However, such SiPOS devices have a drawback due to the slow transient performance caused by the extremely high series resistance in the trench under high frequency switch operations.
This type of structures can only achieve limited performance enhancement due to the lack of lateral charge balance and lack of the drain bias coupling. The devices of this type of structures are also high sensitive to manufacturing variations thus may become unreliable unless the manufacturing processes are well controlled.
The third type of device structures to increase the breakdown voltage is achieved through three-dimensional (3D) charge coupling. FIGS. 3A-1 and 3A-2 show such device structure with biased SiPOS filled trenches used to function as a voltage divider between the drain at a high voltage and the low voltage gate/source region near the top surface. The SiPOS trench filling material is a semiconductor with a high resistance achieved by incorporating oxygen into the silicon. Therefore, the SiPOS is functioning as the resistive elements and not as a charge-storage or a capacitive element. FIGS. 3B-1 and 3B-2 show the functional principles of the structure where the SiPOS constitutes as a resistive connection between the high bias drain and a low bias source. The electric field in the resistors is coupled laterally through capacitive coupling to the adjacent drift region thus resulting in the depletion in the adjacent regions. FIGS. 3C-1 and 3C-2 show another device configuration with stacked and coupled diode (SCD). The PN junction diodes are formed in the trenches as stacked and coupled diodes to enhance the breakdown voltage (U.S. Pat. No. 7,132,712). Such device however has a limitation due to the use of SiPOS that is not available in many foundries or commercial fabrication facilities thus causing inconveniences and also increase the fabrication costs. Furthermore, the disclosures as described above still cannot achieve full three-dimensional charge balance due to the “discrete coupling” as that inherent in these device structures. Furthermore, significant increase of manufacturing cost is required in order to achieve higher number of coupling elements for performance enhancement.
In another Patent Application US20060255401, in order to increase the breakdown voltage with reduced resistance, a device is implemented with insulating trenches that includes a series of capacitive structures extending over an intermediate region between a top surface and a bottom surface of the device. The capacitive structure in the trenches is formed with floating elements composed of particularly selected materials to function as charge coupling in order to achieve charge balance along all directions thus providing a device with a high breakdown voltage and low resistance. However, complicate processes with multiple steps of floating element formation are required to form these floating elements in the trenches thus causing unfavorable impacts to the production cost.
Therefore, a need still exists in the art of semiconductor device design and manufacture to provide new device configurations and manufacturing method in forming the vertical semiconductor devices such that the above discussed problems and limitations can be resolved.